One way of circumventing this difficulty is to use encapsulated chips, i.e. chips placed in a package which may itself be completely tested. Specifically, a package comprises outputs taking the form of solder balls which are spaced further apart than the pads of the chips, for example:                spacing of the chip pads: 50 to 100 μm;        spacing of the ball grid array packages encapsulating a chip: from 400 to 800 μm.        
Test sockets may therefore be used and the packages are thus able to be tested.
In light of this observation, a stacking technology that is suited to these packages and that is able to operate at high frequency must be found.